RISC-V: How an open ISA benefits hardware security | Drew Fustini | Hardwear.io Webinar

About Webinar: ----------------- Ten years after the project was launched inside UC Berkeley, RISC-V is an open instruction set (ISA) that is enabling a growing number of open-source processor implementations. ETH Zurich implemented a RISC-V microcontroller core which has been adopted by non-profit lowRISC for the OpenTitan project in collaboration with Google. This project aims to provide a reference design to build a more transparent and trustworthy Root of Trust chips. I will be exploring this and other security projects that are benefited from open source design at the chip level. About Speaker: --------------- Drew Fustini is a hardware designer and embedded Linux developer. He serves on the board of directors for the Open Source Hardware Association and the BeagleBoard.org Foundation, and is an ambassador for the RISC-V Foundation. Drew designs circuit boards for OSH Park, a PCB manufacturing service, and maintains the Adafruit BeagleBone Python library. #Hardware #Security #Risc_V #Cybersecurity ---------------------------------------------------------------------------------- Website: https://hardwear.io Twitter: https://twitter.com/hardwear_io Facebook: https://www.facebook.com/hardwear.io LinkedIn: https://www.linkedin.com/company/hardwear.io-hardwaresecurityconferenceandtraining/ Instagram: https://www.instagram.com/hardwear.io/